Device for potential-free transmission of data

ABSTRACT

A device for potential-free transmission of dominant and recessive data bits in a bus system operating with bit-by-bit arbitration includes a series connection of a modulator, a galvanic separation circuit, and a demodulator. Data bits to be transmitted are scanned in the modulator at equidistant time intervals and are divided into two intermediate trains of data bits wherein the dominant bits alternate with the recessive bits. The two intermediate trains are applied to two input terminals of a galvanic separating device, and a demodulation is effected on the output side of the separating device.

PRIOR ART

The invention is based on a device for potential-free transmission ofdata in bus networks with bit-by-bit arbitration operating in responseto dominant and recessive bit levels. This is a matter of providing afailure-tolerant bus coupling circuit with galvanic separation ordecoupling, for a local multi-master network with the bit-by-bitarbitration.

A very effective method of bus allocation in local multi-master networksis bit-by-bit arbitration (e.g. CAN, ICC, DDB).

Multi-master networks with bit-by-bit arbitration operate with thelogical bit levels which are physically represented on the bus by`dominant` and `recessive` states. The recessive bit level on the buscan be overwritten at any time by means of transmitting the dominant bitlevel. The bus content is decided in that the transmitter bus of arecessive bit during the simultaneous sensing of a dominant bit gives upthe contest and becomes the receiver bus.

With this concept, the DC component of the signals is included in thetransmission via the line.

Examples of these physical representations of logical bit levels on thebus are:

    ______________________________________                                        `dominant` bit level                                                                             `recessive` bit level                                      ______________________________________                                        low-impedance      high-impedance                                             light on           light off                                                  voltage on         no voltage                                                 power on           no power                                                   ______________________________________                                    

In the prior art networks with bit-by-bit bus arbitration,optoelectronic components must be used for galvanic decoupling orseparation of the individual substations at least on the transmittingside, since these optoelectronic components can include the DC componentin the transmission:

opto-coupler for coupling at a bus with electrical line;

optical transmitter and receiver at a light wave-guide bus with starcoupler.

Opto-couplers are components with relatively high failure rates whichcan not be used at extreme temperatures or at rapid changes intemperature.

Because of the required `dominant` and `recessive` bit levels, onlyopto-couplers with open collector outputs are taken into considerationfor the target network. During breakdown of this output transistor the`dominant` bit level is generated, and the entire network is blocked.

Optical transmitters and receivers at the light waveguide with starcoupler are too expensive and too unreliable for use in motor vehiclenetworks.

The limitations in the use of light guides and optical plug-in contactsdo not at present allow use under extreme conditions (e.g. in motorvehicles).

If light (`dominant` bit level) is continuously produced during thefailure of a driver of the transmitting element, the entire network isblocked. During failure of the star coupler the network is likewiseblocked.

It is the object of the invention to provide a device for potential-freetransmission of data which does not block the transmission path duringthe failure of a station and is reliable and inexpensive with respect toits use in large quantities, particularly in motor vehicles.

ADVANTAGES OF THE INVENTION

An electrical potential separation between the input and output of thedevice of this invention is achieved so that network stations equippedwith the device can also be operated when the individual stations are atdifferent potentials or when strong inphase interferences occur on thebusline.

Differential interferences which are imported into the respectivestation via the busline are decoupled (positive differentialinterference) or limited (negative differential interference),respectively, at the demodulator. The circuit blocks located after thedemodulator as seen from the busline, are accordingly protected fromdestruction.

During failure or short circuiting of a block of the coupling circuitprior to the separating device, e.g. of a driver or interface block, thebus traffic on the busline between the remaining station is notimpaired, since the bus is decoupled by means of the separating deviceand demodulator.

The device is very reliable and inexpensive, so that it can be used e.g.in motor vehicles.

BRIEF DESCRIPTION OF THE DRAWING

Embodiment examples of the invention are shown in the drawing and areexplained in more detail in the following description.

FIG. 1 shows a block diagram of the device of the invention inconnection with the overall bus system of a global or main network, e.g.in a motor vehicle;

FIG. 2 shows a time-dependent diagram for the operation of the device;

FIG. 3 shows two embodiments of a modulation encoder for the device;

FIG. 4 shows example of a driver circuit for the device;

FIG. 5 shows an example of a local network;

FIG. 6 shows examples of the galvanic separation circuit;

FIG. 7 shows circuit arrangement for the demodulation;

FIG. 8 shows a circuit arrangement for a bus coupling network;

FIGS. 9 and 10 show embodiment of the device of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

a) Bus System

FIG. 1 shows the block diagram of the overall bus system of a mainnetwork for use in a power supply system of a motor vehicle.

It comprises master bus stations 1, 2, 3 in connection with a global ormain network 4. The master bus stations 1, 2, 3 are connected to themain network 4 via the bus lines 41, 42, 43. Every master bus stationcomprises modulation encoder 10, driver 20, local network 30, galvanicseparation circuit 40, demodulator 50 and bus coupling network 60. Thesignal to be transmitted is generated by an interface block 7 and isavailable at bus line 101. The interface block 7 also processes thereceived signal which is present at line 71, possibly modified by meansof additional blocks.

b) Description of a Master Bus Station (using bus station 1 by way ofexample)

The digital signal to be transmitted from the interface block 7 isapplied via the lines 101 to the modulation encoder 10. The latterproduces two intermediate code signals without DC component (FIGS. 2cand 2d) from the input signal with DC component (FIG. 2b). The outputsof the modulation encoder 10 are connected via lines 201 to the inputsof the driver 20. The outputs of the driver 20 are connected to theinputs of the local network 30 via lines 301. This network 30 cancomprise additional inputs 302, 303 etc. in order to couple with oneanother interface blocks and application circuits of additionalsubstations each having a corresponding modulation encoder and driver.The outputs of the local network 30 are connected via lines 401 to theinputs of the galvanic separation circuit 40. The outputs of thegalvanic separation circuit 40 are applied to the inputs of thedemodulator 50 via lines 501. A signal with DC component is generatedagain in the demodulator from the galvanically decoupled or separatedintermediate code signals without DC component. The outputs of thedemodulator 50 are connected to the inputs of the bus coupling network60 via lines 601. The outputs of the bus coupling network 60 areconnected to the inputs of the main network 4 via the bus lines 41;moreover, a signal received at the output of the network 60 is fed fromthis location via lines 71, possibly via additional (non-illustrated)blocks, to the interface block 7. This interface block 7 assembles theread bits of the fed back signal and transmits the resulting data vialine 6 to the application circuit 5. Many participating master busstations can be interconnected by the main network 4 over a greaterdistance.

The local network 30 can also be dispensed with. The outputs 301 of thedriver 20 are then connected directly to the inputs 401 of the galvanicseparation circuit 40.

Modulation encoder 10 and driver 20 can also be integrated in theinterface block in an inexpensive manner. For this reason, themodulation encoder and driver are directly connected with the interfaceblock.

An example of the manner of operation of the transmission device of theinvention is shown in FIG. 2 with the aid of the time-dependent diagram.FIG. 2a shows the clock signal having a frequency at which theprocessing of the arriving data to be transmitted is effected in themodulation encoder 10. The signal to be transmitted is shown in FIG. 2b.Changes in the bit level are possible in each instance only insynchronism with the clock pulses. The signal to be transmitted isconverted by means of the modulation encoder 10 into two intermediatecode signals shown in FIG. 2c and FIG. 2d, which serve to control agalvanic separating element. These intermediate code signals, accordingto FIG. 2c and FIG. 2d, are both at logical `0` during the transmissionof a recessive bit, but are alternately at logical `0` and logical `1`when transmitting a dominant bit. In other words, time intervals of thedominant single bit levels of one intermediate code signal (FIG. 2c)coincide with time intervals of the recessive single bit levels of theother intermediate code signal (FIG. 2d), and time intervals of thedominant single bit levels of the other intermediate code signalcoincide with time intervals of the recessive single bit levels of theone intermediate code signal. FIG. 2e shows the `modulated` intermediateoutput signal after the galvanic separation. In this instance, there isa positive voltage +4 during each dominant bit of the intermediate codesignal of FIG. 2c and a negative voltage 4 during each dominant bit ofthe other intermediate code signal (FIG. 2d), but zero voltage duringcoincidence of a recessive bit in both intermediate code signals. Afterthe demodulation of the `modulated` output signal, the original signalconfiguration, as shown in FIG. 2f, is obtained again. The result is apotential-separated transmission of a signal which corresponds withrespect to its configuration to the original transmitted signalaccording to FIG. 2b.

Embodiment examples of the individual component blocks of the device ofthe invention incorporated in the bus stations of the system, accordingto FIG. 1, are described in more detail in the following.

c) Modulation Encoder

FIGS. 3a and 3b show two embodiment examples for the modulation encoder10.

The modulation encoder 10 has the object of preparing the signal to betransmitted for the connection to a galvanic separating element. Thetransmitted signal (FIG. 2b) is acted upon by the clock signal (FIG. 2a)which acts as a modulation code carrier for this purpose. The latter canadvisably have the same frequency as the bit clock of the transmittedsignal or can have a higher frequency.

It is possible to let the modulation encoder run freely or tosynchronize it, e.g. to start the modulation encoders of all bussubstations in the same manner at the start of each transmission. Asynchronization ensures that the intermediate code signals of all bussubstations are in the same phase. This is necessary if the intermediatecode signals of a plurality of substations are coupled in the localnetwork 30.

FIG. 3a shows an embodiment example of an unsynchronized modulationencoder.

The transmitted signal is applied to the input line 1011 and is appliedto the D-input of a D-flip-flop 102 and to the T-input of a toggleflip-flop 103. The clock signal reaches the clock inputs of the twoflip-flops 102 and 103 via the input line 1012. The Q-output of theD-flip-flop 102 is applied to one input of the logical AND gates 104 and105 in each instance and also leads to the output line 2011. TheQ-output of the toggle flip-flop 103 is applied to the second input ofthe AND gate 104, the Q-inverted output is applied to the second inputof the AND gate 105. The outputs of the AND gates 104 and 105 form theoutput lines 2012 and 2013. Operation:

The D-flip-flop 102 and the toggle flip-flop 103 are clocked with theclock signal; the transmitted signal is applied to the D- and T-inputs,respectively, of the two flip-flops. In this case, the `dominant` levelis a logical `1` and the `recessive` level is a logical `0`. TheD-flip-flop 102 synchronizes the transmitted signal according to theclock signal. The toggle flip-flop 103 changes state at a `dominant`transmitted signal with every clock pulse edge, so that its Q- andQ-inverted outputs change polarity with every clock pulse. By means ofthe AND gating relation of the Q- and Q-inverted outputs of the toggleflip-flop with the synchronized transmitted signal, it is achieved thatthe output lines 2012 and 2013 are both at logical `0` during thetransmission of a `recessive` bit, but when transmitting a `dominant`bit are alternately at logical `0` and logical `1` in the time intervalsof the clock signal.

FIG. 3b shows an embodiment example of a synchronized modulationencoder.

In contrast to the unsynchronized modulation encoder according to FIG.3a, the toggle flip-flop in this instance is reset by means of asynchronization signal. For this purpose, the synchronization signal isapplied to the `reset` input of the toggle flip-flop 106 via the line1013. The synchronization signal can be e.g. a short pulse at the startof a new communication.

The outputs of this modulation encoder behave logically in the same wayas in the unsynchronized modulation encoder; the phase relation of themodulation encoder outputs 2012 and 2013 in this instance isadditionally defined with respect to all other modulator encoderoutputs, also synchronized outputs, and are connected to the localnetwork 30.

d) Driver

FIGS. 4a and 4b show respectively embodiment examples for an opencollector driver and for a push-pull driver. Such a push-pull driver isobtainable e.g. under the designation SN74126 from the company TEXASINSTRUMENTS.

The type of driver utilized depends on the manner in which the galvanicseparation circuit is carried out. When a transformer with a center tapon the primary side is used, e.g. an open collector driver is used; apush-pull driver is used in a transformer without center tap on theprimary side.

FIG. 4a shows an embodiment example of an open collector driver.

The input intermediate code signals FIGS. 2c and 2d coming via lines2012 and 2013 from the modulation encoder 10 are guided to the baseterminals of the n-p-n transistors 204 and 205 via the resistors 202 and203. The emitter terminals of the transistor 204 and 205 are applied toground potential. The collector terminals are connected with the outputlines 3011 and 3012. The amplified signal can be taken off at thelatter.

FIG. 4b shows an embodiment example of a push-pull driver.

In this instance the input signals coming via lines 2012 and 2013 fromthe modulation encoder 10 are applied to the signal inputs of twopush-pull drivers 206 and 207. The drivers are tri-state drivers whichcan be switched to high impedance via the line 2011 to which thetransmitted signal, which is synchronized with the modulator clocksignal, is applied. The outputs of the two push-pull drivers 206 and 207are connected to the output lines 3011 and 3012.

e) Local Network

FIG. 5 shows an embodiment example for a passive local network 30.

The driver outputs (3011, 3012), (3021, 3022), respectively, and (3031,3032) of the individual local substations are connected via resistors306 . . . 311 to the local buslines 304 and 305 in the same direction.The outputs 4011 and 4012 are likewise connected to the buslines 304 and305 via the resistors 312 and 313. The resistors 306 . . . 311 and 312,313, respectively, can be dispensed with if desired.

f) Galvanic separation circuit

FIGS. 6a to 6c show some embodiment examples for the galanic separationcircuit 40.

FIGS. 6a and 6b show two constructions of galvanic separation by meansof transformers, while FIG. 6c shows a galvanic separation by means ofcapacitors.

FIG. 6a shows a transformer 402 with single primary and secondarywindings for galvanic separation. The input intermediate code signalsare applied via lines 4011 and 4012 respectively to the primary windingof the transformer, while the secondary winding is connected with theoutput lines 5011 and 5012 delivering the `modulated` output signal ofFIG. 2e.

FIG. 6b shows a transformer 403 with center tap on the primary andsecondary windings for galvanic separation. The input lines 4011 and4012 are applied to the outer connections of the primary winding, theinput line 4013 is applied to its center tap. The outer connections ofthe secondary winding are connected with the ouptut lines 5011 and 5012,the center tap is connected with the output line 5013.

In the galvanic separation circuits according to FIGS. 6a and 6b,inphase interferences which can occur on the busline are blocked by thetransformer. They can not reach the primary side of the transformer.

Two capacitors 404, 405 are used in the four terminal capacitor circuitof FIG. 6c for galvanic separation. The input lines 4011 and 4012 areconnected with the output lines 5011 and 5012 via the two capacitors 404and 405.

g) Demodulator

FIGS. 7a and 7b show two embodiment examples for the demodulator 50.

FIG. 7a shows a Graetz or bridge rectification. The input terminals ofthe bridge 502 are connected via lines 5011 and 5012 to the outputs ofthe galvanic separation 40. The demodulated signal (FIG. 2f) isavailable at the outputs 6011 and 6012 of the Graetz rectifier 502.

FIG. 7b shows a demodulator which is preferably connected to the outputof a transformer (FIG. 6b) with a center tap on the secondary side. Inthis instance, the lines 5011 and 5012, are connected with the outputline 6011 of the demodulator via the rectifying diodes 503 and 504. Thecenter tap line 5013 arrives directly at the output line 6012.

h) Bus Coupling Network

FIG. 8 shows an embodiment example for the bus coupling network 60.

The input lines 6011 and 6012 are applied to the output lines 411 and412 via the resistors 602 and 603. A Zener diode 604 can be connectedbetween the output lines 411 and 412.

This diode prevents extreme bus levels from occurring outside the wantedsignal range. Differential bus interferences are accordingly clippedoff; moreover, reflections on the busline which can occur due to faultyterminations are dampened.

FIG. 9 and 10 show two embodiment examples of a bus stationincorporating the device of the invention. The blocks 7, 10 and 20 areintegrated in an interface module 8 (e.g. CAN-controller module). Thus,only a few external component elements are necessary, which enables aninexpensive realization.

FIG. 9 shows an embodiment example of a bus system or station withgalvanic decoupling circuit 40 using a transformer according to FIG. 6aand subsequent demodulator 50 using Graetz rectification according toFIG. 7a. The interface 7, the modulation encorder 10 according to FIG.3a and the driver 20 according to FIG. 4b are integrated in theinterface module 8.

ADVANTAGES OF THE ARRANGEMENT ACCORDING TO FIG. 9

Inphase interferences on the busline can not cause any differentialsignal on the secondary side of the transformer, i.e. its effects cannot reach the primary side of the transformer and the interface module8.

Positive differential interferences on the busline have no effect on thetransmitting side, since all diodes of the rectifier are in blockingcondition.

Negative differential interferences do not cause any differential signalat the transformer, since all diodes of the Graetz rectifier areconductive and accordingly the two connections of the secondary windingare at the same potential.

During failure of one or both drivers or when there is a shorted coil ofthe transformer at the primary or secondary side, the remaining bustraffic on the busline is not impaired, since the bus is decoupled bymeans of the rectifier.

FIG. 10 shows an embodiment example of a bus system or station withgalvanic decoupling using a transformer having center taps on theprimary and secondary sides according to FIG. 6b and subsequentfull-wave rectification according to FIG. 7b. The modulation encorderaccording to FIG. 3a and the driver according to FIG. 4a are integratedin an interface module 8. The block 9, which contains blocks equivalentto 5 and 8, is added as an embodiment example for a local network orsubstation.

ADVANTAGES OF THE ARRANGEMENT ACCORDING TO FIG. 10

Inphase interferences on the busline can not cause any differentialsignal on the secondary side of the transformer, i.e. its effects cannot reach the primary side of the transformer.

Positive differential interferences on the busline have no effect on thetransmitting side, since all diodes of the rectifier block.

Negative differential interferences do not cause any differential signalat the transformer, since two currents of the same magnitude flow inopposite directions in the secondary winding.

During failure of one or both drivers or when there is a shorted coil ofthe transformer at the primary or secondary side, the remaining bustraffic on the busline is not impaired, since the bus is decoupled bymeans of the rectifier.

When there are a plurality of local substations the separating deviceand the demodulator are needed only once, which enables a particularlyinexpensive solution.

We claim:
 1. A device for potential-free transmission of data in a busnetwork with bit-by-bit arbitration operation in response to dominantand recessive bit levels, comprising a series connection of a means fordelivering a digital signal to be transmitted, a modulation encoder forscanning dominant levels of said digital signal at equidistant timeintervals and delivering two intermediate signals with alternatingdominant and recessive single bit levels in the place of scannedportions of said dominant levels; a galvanic separating device forreceiving at its inputs said intermediate signals and delivering at itsoutputs an intermediate output signal which is galvanically separatedfrom the input intermediate signals and free of D.C. components; and ademodulator for converting the intermediate output signal into ademodulated signal which corresponds in shape to said digital signal tobe transmitted.
 2. A device according to claim 1, characterized in thatthe decoupling device is a transformer with at least two inputconnections.
 3. A device as defined in claim 1, further comprising alocal coupling network, connected between said modulation encoder andgalvanic separating device for receiving intermediate signals frommodulation encoder of additional potential-free transmission devices. 4.A device as defined in claim 1, further comprising driver circuitsconnected between said modulation encoder and said galvanic separatingdevice.
 5. A device as defined in claim 4, wherein said driver circuitsare tri-state drivers.
 6. A device as defined in claim 4, wherein saiddriver circuits are transistors with open collector outputs connected tosaid separating device.
 7. A device according to claim 1, characterizedin that a multi-path rectifier, particularly a full-wave or bridgerectifier, is provided as a demodulator.
 8. A device according to claim7, characterized in that a voltage-dependent element, particularly aZener diode, is arrange on the output side of the rectifier.
 9. A deviceaccording to claim 1, characterized in that a transformer with centertapping is used as a decoupling device.
 10. A device according to claim1, characterized in that a capacitor four-terminal is used as adecoupling device.
 11. A device as defined in claim 1, wherein saidmodulation encoder comprises a clock signal generator, a D-flip-flop, aT-flip-flop and two AND gates, said digital signal to be transmitted isfed to signal inputs of the two flip-flops, said clock signal generatorbeing connected to clock-inputs of the two flip-flops, one input of thetwo AND gates being connected to the Q-output of said D-flip-flop, theother input of one of said AND gates being connected to the Q-output ofsaid T-flip-flop, the other input of the other AND gate being connectedto the Q-output of said T-flip-flop, and the outputs of respective andgates delivering said intermediate signals.
 12. A device as defined inclaim 1, wherein time intervals of the dominant single bit levels of oneintermediate signal coincide with time intervals of the recessive singlebit levels; and time intervals of the dominant single bit levels of theother intermediate signal coincide with time intervals of the recessivesignal bit levels of the one intermediate signal.
 13. A device asdefined in claim 12, wherein the intermediate output signal includes apositive voltage during each dominant bit of the one intermediate signaland a negative voltage during each dominant bit of the otherintermediate signal, and zero voltage during coincidence of a recessivebit in both intermediate signals.